Examples of a conventional AGC circuit not requiring an integrator circuit using a capacitor and easily contained in an integrated circuit are a gain control circuit disclosed in Japanese Laid-Open Patent Publication No. 60-123115 and an AGC circuit proposed by the present Applicant in Japanese Laid-Open Patent Publication No. 2004-274571.
FIG. 20 illustrates the exemplified conventional AGC circuit described in Japanese Laid-Open Patent Publication No. 2004-274571. In FIG. 20, a reference sign A1 denotes a signal input terminal to which an input signal VA is supplied. A reference numeral 101 denotes a variable gain amplifier that outputs an output signal VB by amplifying or attenuating the voltage of the input signal VA in accordance with its gain controlled in accordance with a gain control voltage V108. A reference sign B1 denotes a signal output terminal for outputting the output signal VB of the variable gain amplifier 101. A reference numeral 102 denotes a rectifier for rectifying the output voltage of the variable gain amplifier 101. A reference numeral 103 denotes a voltage comparator that compares a rectified signal having been rectified by the rectifier 102, namely, an output signal V101, with an arbitrary threshold voltage V102 precedently determined for outputting an output signal V103 at a high level when the output signal V101 is higher than the threshold voltage V102 and outputting the output signal V103 at a low level when the output signal V101 is lower than the threshold voltage V102. A reference numeral 104 denotes a threshold voltage input terminal through which the threshold voltage V102 is input to the voltage comparator 103. A reference numeral 105 denotes an up/down counter. A reference numeral 106 denotes a count control terminal for inputting the output voltage V103 of the voltage comparator 103 as a control signal V104 for controlling an up-count operation and a down-count operation. A reference numeral 107 denotes an up-count clock terminal for inputting an up-count clock signal V105. A reference numeral 108 denotes a down-count clock terminal for inputting a down-count clock signal V106. A reference numeral 109 denotes a D/A converter section for outputting a DC output voltage V107 in accordance with the count value of the up/down counter 105. A reference numeral 110 denotes a DC amplifier having an arbitrarily set gain, receiving the DC output voltage V107 of the D/A converter section 109 as an input signal and outputting the gain control voltage V108.
The operation of the conventional AGC circuit having the aforementioned configuration will now be described with reference to an accompanying drawing.
FIG. 21 illustrates the output signal VB of the variable gain amplifier 101, the output voltage V101 of the rectifier 102, the output voltage V103 of the voltage comparator 103, the up-count clock signal V105, the down-count clock signal V106 and the DC output voltage V107 of the D/A converter section 109. Incidentally, it is assumed for simplifying description that each of the up-count clock signal V105 and the down-count clock signal V106 is a clock pulse with a constant frequency and that the output signal VB is a sine wave.
In FIG. 21, the output signal VB having a sine wave waveform of the variable gain amplifier 101 is rectified by the rectifier 102. The output voltage V101 of the rectifier 102 attains a pulsating waveform and is input to the voltage comparator 103. The voltage comparator 103 compares the output voltage V101 of the rectifier 102 with the precedently set threshold voltage V102. As a result, the output voltage V103 of the voltage comparator 103 attains a pulse waveform. The thus obtained output voltage V103 of the voltage comparator 103 works as the control signal V104 for the up-count operation and the down-count operation of the up/down counter 105, so as to be input to the count control terminal 106 of the up/down counter 105.
On the other hand, the up-count clock terminal 107 of the up/down counter 105 is supplied with the up-count clock signal V105 and the down-count clock terminal 108 is supplied with the down-count clock signal V106.
The up/down counter 105 performs the up-count operation according to an up-count frequency set in accordance with the up-count clock signal V105 in a period T1 when the voltage on the count control terminal 106 is at a high level. Alternatively, in a period T2 when the voltage on the count control terminal 106 is at a low level, it performs the down-count operation according to a down-count frequency set in accordance with the down-count clock signal V106. Therefore, the up/down counter 105 alternately repeats the up-count and the down-count, and hence, the D/A converter section 109 outputting a DC voltage in accordance with the count value C of the up/down counter 105 outputs the DC output voltage V107 as illustrated in FIG. 21.
The DC output voltage V107 of the D/A converter section 109 is amplified by the DC amplifier 110 to arbitrary magnitude to be used as the gain control voltage V108 for the variable gain amplifier 101. The gain of the variable gain amplifier 101 is changed in accordance with the gain control voltage V108 so as to amplify or attenuate the input signal VA.
When the DC output voltage V107 of the D/A converter section 109 is increased, the gain of the variable gain amplifier 101 is lowered and the level of the output signal VB is lowered, and hence, the down-count is proceeded. Therefore, the DC output voltage V107 of the D/A converter section 109 is lowered, and hence, the gain of the variable gain amplifier 101 is increased in turn. As a result, the level of the output signal VB is increased, and hence, the up-count is proceeded. By repeating this cycle, the level of the output signal VB of the variable gain amplifier 101 is converged at a constant level.